Title:
INFORMATION PROCESSOR AND INFORMATION PROCESSING METHOD CAPABLE OF SUPPRESSING BRANCH PREDICTION
Document Type and Number:
Japanese Patent JP3683439
Kind Code:
B
Abstract:
PROBLEM TO BE SOLVED: To improve the prediction of the action of an event wait branch loop and to accelerate the escape speed of the loop concerning an information processor for performing pipeline processing with branch prediction.
SOLUTION: When the branching instruction of event wait is detected, a decoder 110 asserts a signal DNO-PRD. Corresponding to this assert, an AND circuit 11 negates a signal D-HINT for branch prediction and an AND circuit 112 negates a write signal E-PC of a branch prediction table 23. Therefore, the branch prediction is suppressed and the prefetch of an instruction following the branching instruction is promoted.
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Inventors:
Nakada, Tatsuki
Application Number:
JP1999000236553
Publication Date:
June 03, 2005
Filing Date:
August 24, 1999
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F9/38; G06F9/00; G06F9/30; G06F9/308; G06F9/32; (IPC1-7): G06F9/38; G06F9/30
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