Title:
INFORMATION PROCESSOR
Document Type and Number:
Japanese Patent JP2005215911
Kind Code:
A
Abstract:
To further improve the processing performance of an information processor while keeping a cache capacity or a main storage configuration in the same state.
Instead of directly connecting a block map circuit to the output of an arithmetic unit, a first block map circuit is mounted between the arithmetic unit and a data cache, so that an address not subjected to block map is carried to an internal bus. Thereafter, a second block map circuit is mounted on an external memory control circuit. Accordingly, the mapping patterns of the first block map circuit and the second block map circuit can be independently set.
Inventors:
TANAKA KAZUHIKO
HOSOKI KOJI
EHAMA MASAKAZU
NAKADA KEIMEI
HOSOKI KOJI
EHAMA MASAKAZU
NAKADA KEIMEI
Application Number:
JP2004020687A
Publication Date:
August 11, 2005
Filing Date:
January 29, 2004
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F12/08; (IPC1-7): G06F12/08
Domestic Patent References:
| JPH08297605A | 1996-11-12 | |||
| JP2002500394A | 2002-01-08 | |||
| JPH11143774A | 1999-05-28 | |||
| JPH0553909A | 1993-03-05 | |||
| JP2001243112A | 2001-09-07 | |||
| JPH09223067A | 1997-08-26 | |||
| JP2001022638A | 2001-01-26 | |||
| JP2000293437A | 2000-10-20 | |||
| JP2000276588A | 2000-10-06 |
Attorney, Agent or Firm:
Yasuo Sakuta
Manabu Inoue
Manabu Inoue
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