To accurately acquire instruction execution analysis information and memory access information of CPUs.

An information processor comprises: central processing units (CPU#0 and #1) which include execution parts (103 and 203) coupled to operand buses (105 and 205), and control parts (101 and 201); and a debug circuit (35). The control parts include a debug function unit for collecting instruction execution analysis information of the central processing unit. The debug circuit includes: trace acquisition circuits (110 and 210) for capturing the instruction execution analysis information and information acquired through the operand busses via their respectively dedicated logical circuits (112, 114, 212, and 214); and trace output circuits (111 and 211). The trace acquisition circuits include rearrangement logic parts (115 and 215) for rearranging the instruction execution analysis information and the information acquired through the operand busses, allowing accurate tracing.