Title:
INFORMATION PROCESSOR
Document Type and Number:
Japanese Patent JP3545252
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve the reliability of an information processor having plural CPUs.
SOLUTION: When a fault occurs in any one of storage devices 10 to 13, its corresponding control device informs other control devices of the fault occurrence, so that all control devices 4 to 7 can recognize the fault occurrence. When any one of CPUs 1a, 1b, 2a, 2b accesses the storage device, the control device informs the CPU of the fault occurrence. The CPU receiving the information changes the storage device to be used for a working system if necessary on the basis of a prescribed rule. Similar processing is executed also in a case that another CPU accesses the storage device, so that the setting of the working system is completed when all the CPUs execute accesses.
Inventors:
Shinichi Onizuka
Toshinori Hiraishi
Akihiko Hisada
Noriaki Shimizu
Noboru Izumi
Toshinori Hiraishi
Akihiko Hisada
Noriaki Shimizu
Noboru Izumi
Application Number:
JP8745699A
Publication Date:
July 21, 2004
Filing Date:
March 30, 1999
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F12/16; G06F9/46; G06F11/00; G06F11/20; G06F15/16; G06F9/48; (IPC1-7): G06F12/16; G06F15/16
Domestic Patent References:
| JP58070495A | ||||
| JP2058140A | ||||
| JP6019635A |
Attorney, Agent or Firm:
Takeshi Hattori