PURPOSE: To further shorten bus cycle so as to improve processing performance.

CONSTITUTION: In a control processing unit 1, parity check circuit 11 performs parity checking and if parity error is detected, a signal 1000 informs a bus cycle control circuit 12 of it. The bus cycle control circuit 12 makes a re- transfer requesting signal 101 active far informing a main storage 2 of it. The main storage 2 prevents the data and parity outputted from a main storing part 20 from sent to a bus 3 when the retransfer requesting signal 101 becomes active, and the data and parity having been subjected to one-bit correction from an ECC circuit 21 are outputted to the bus 3.