Title:
INFORMATION PROCESSOR
Document Type and Number:
Japanese Patent JPH0619801
Kind Code:
A
Abstract:
PURPOSE: To permit a processor having no parity and I/O having the parity to exist on the same bus and to access a memory so that they can access the common memory.
CONSTITUTION: A memory controller 16 provided between common RAM is provided with a bus arbitration block 21 arbitrating the bus and generating a bus state signal showing a bus master, a write data latch 22, a parity checker 231, a parity generator 232, a selector 24, an RDY generation block 25, an input/output buffer 27 and a memory control signal generation block 29. On memory writing, the memory controller judges whether the bus master has the parity or not and accordingly checks or generates the parity as against data.
Inventors:
HIRAHATA KENJI
FUJIGAMI YOSHIHIRO
WATABE KEN
ENOMOTO HIROMICHI
FUJIGAMI YOSHIHIRO
WATABE KEN
ENOMOTO HIROMICHI
Application Number:
JP17577292A
Publication Date:
January 28, 1994
Filing Date:
July 02, 1992
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F11/08; G06F12/16; G06F13/32; G06F13/36; (IPC1-7): G06F12/16; G06F11/08; G06F13/32
Attorney, Agent or Firm:
Kazuko Tomita
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