PURPOSE: To shorten the period of a clock in confirmity to the internal processing speed of a microprocessor by switching and controlling the period of the clock between microprocessor internal processing cycles and external interface control cycles.

CONSTITUTION: In machine cycles including memory reading operation, a microprocessor 10 outputs a memory address to an ADRESS line in a basic cycles T1 and, while holding a signal RD at a "0" in the next basic cycle T2, permits a clock control part 11 by a control signal CONTROL to change the period of a clock CLK' over to a tC2. Then, it is confirmed that a signal READY is a "1" and the processor enters into the next basic cycle T3 to read memory readout data onto a line DATA. Therefore, it is unnecessary to consider the cycle time, etc., of a memory as to the period tC2 of the clock CLK', and they can be shortened sufficiently in conformity to the internal processing speed of the microprocessor 10, shorten the machime cycles.