Title:
INFORMATION REPRODUCING DEVICE AND ITS BIT ERROR MEASURING DEVICE
Document Type and Number:
Japanese Patent JPH05325433
Kind Code:
A
Abstract:
PURPOSE:To easily detect a bit error by adding the minimum number of circuits, and to easily realize the measurement of a bit error rate at a low cost. CONSTITUTION:A reproducing is A/D-converted, and outputted to a Viterbi decoder 52 and a ternary level detecting circuit 53. The Viterbi decoder 52 and the ternary level detecting circuit 52 are constituted as one circuit for realizing simultaneously these functions, and a comparing circuit 54 compares results of decoding, regards a different one as an error outputs a result of error detection to a counter 55. The counter 55 counts the number of errors based on a command from a control circuit 56, and outputs a result of counting as the number of errors. The number of detected bit errors is roughly equal to the number of errors at the time when a ternary level detection is executed. The result of actual decoding uses that which is subjected to Viterbi decoding, therefore, by having their conversion table, to what extent an error is contained in an output from the Viterbi decoder 52 can easily be estimated.
Inventors:
HAYASHI NOBUHIRO
Application Number:
JP15750792A
Publication Date:
December 10, 1993
Filing Date:
May 25, 1992
Export Citation:
Assignee:
SONY CORP
International Classes:
G11B20/18; (IPC1-7): G11B20/18; G11B20/18
Attorney, Agent or Firm:
Mitsuo Takahashi