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Title:
INFORMATION SECURITY DEVICE, EXPONENTIATION ARITHMETIC UNIT, EXPONENTIATION REMAINDER ARITHMETIC UNIT, AND ELLIPTIC EXPONENTIATION MULTIPLE ARITHMETIC UNIT
Document Type and Number:
Japanese Patent JP2002358012
Kind Code:
A
Abstract:

To provide an information security device which executes a quick exponentiation arithmetic method like the small window method without enlarging the circuit scale of a coprocessor neither a memory.

A relatively large table required for the small window method which quickly performs exponentiation arithmetic is prepared on the outside of the coprocessor, and selection of a value from the table and transfer to the coprocessor are performed in parallel with multiple length arithmetic in the coprocessor. Two banks are prepared in the coprocessor as areas for multiple length values used for arithmetic, and one bank is used for arithmetic in the coprocessor while the other is used for data transfer. Banks are switched immediately when arithmetic in the coprocessor is terminated, and data transfer for next arithmetic is performed simultaneously with use of the already transferred value for arithmetic in the coprocessor.


Inventors:
Ono, Takatoshi
Matsuzaki, Natsume
Nakano, Toshihisa
Application Number:
JP2002000077843
Publication Date:
December 13, 2002
Filing Date:
March 20, 2002
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G09C1/00; G09C1/00; (IPC1-7): G09C1/00