PURPOSE: To simplify the control of the address setting timing by using the synchronizing signal included in a restored information signal to control the address setting timing when the information signal is digitized, stored and read out.

CONSTITUTION: The input composite picture signal is stored in a memory 6 by an A/D converter 4 based on the clock signal which is supplied by a clock signal generating circuit 20 via a changeover switch 23. The read addresses are successively designated via the memory 6 so that the composite picture data stored in the designated address is supplied to a D/A converter 8. Then the converted analog composite picture signal is outputted via an output terminal 10 and also supplied to a composite synchronizing signal separator 50. The address setting timing of an address counter 51 is controlled synchronously with the synchronizing signal detected by the separator 50. Thus the constitution of an information signal processor is simplified.