PURPOSE: To initialize a volatile memory in electric power recovery without destroying the contents of a nonvolatile memory by inhibiting transmission of a parity error to a main memory device while the initialization is in process.

CONSTITUTION: In data processor 8 for recovery processing of an electric power break, the output of decoder 9 controlling arithmetic circuit 10 sets flip-flop 11. This set signal is applied as a parity-error detection inhibition signal to gate 4 of main memory unit 1. Readout data from main memory cell 2 consisting of volatile and nonvolatile memories is sent to data processor 8 via parity circuit 3, but while the above-mentioned parity-error detection inhibition signal appears, an error signal is not sent to processor 8. When an error occurs, on the other hand, parity circuit 3 sets a correct parity bit and rewrites main memory cell 2. After the above-mentioned initialization, decoder 9 resets FF11 and places the processing operation in a normal state.