Title:
注入同期型ＰＬＬ回路
Document Type and Number:
Japanese Patent JP6829401
Kind Code:
B2
Abstract:
A PFD outputs a detection signal based on a phase difference or a frequency difference between a reference signal and a feedback signal, a charge pump circuit outputs a pulse signal based on the detection signal, and a loop filter outputs a control voltage based on the pulse signal. A VCO includes a ring oscillator where a plurality of delay element units, which include a plurality of delay elements (for example, inverter circuits) connected in parallel, are connected in series in a ring, controls the frequency of the output signal of the ring oscillator based on the control voltage, and controls the phase of the output signal of the ring oscillator by controlling the active number of delay elements, out of the plurality of delay elements, based on the detection signal. A frequency divider circuit generates and outputs a feedback signal by dividing the frequency of the output signal.
Inventors:
Ichi Sato
Kenta Ariga
Kenta Ariga
Application Number:
JP2018530256A
Publication Date:
February 10, 2021
Filing Date:
July 27, 2016
Export Citation:
Assignee:
Socionext Inc.
International Classes:
H03L7/099; H03K3/354; H03L7/083
Domestic Patent References:
| JP2013179590A | ||||
| JP2007013950A | ||||
| JP53144243A | ||||
| JP2012516092A |
Foreign References:
| US6157691 |
Attorney, Agent or Firm:
Fuso International Patent Office