Title:
INPEDANCE COMPENSATION CIRCUIT
Document Type and Number:
Japanese Patent JP3120580
Kind Code:
B2
Abstract:
PURPOSE: To keep the impedance of a reception circuit being high even at the time of cutting off power source by compensating the reduction in the impedance at the time of power source cut-off due to a parasitic element with two externally mounted diodes.
CONSTITUTION: When a forward voltage of a diode 107 is set to be a value be lower than a base-emitter voltage VBE of an NPN transistor(TR), the TR 203 keeps the OFF state, since the VBE of the TR 203 is suppressed to lower than a voltage at which the TR is turned on. When the TR 203 keeps the OFF state, since no base current flows through an NPN TR 204, the TR 204 keeps the off-state. The impedance at the time of viewing an input A from an input B while the TRs 203, 204 are turned off is a series impedance comprising a resistive element 201 and a diode 107, nearly equal to the resistance of the element 201, and then a high impedance is obtained. A diode 106 acts like keeping the impedance similarly at the time of viewing the input B from the input A to be a high impedance.
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Inventors:
Akio Kurobe
Application Number:
JP21247292A
Publication Date:
December 25, 2000
Filing Date:
August 10, 1992
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F13/00; H04B1/18; H04L25/02; (IPC1-7): H04L25/02; H04B1/18
Domestic Patent References:
| JP6025353A | ||||
| JP58195315A | ||||
| JP36390U | ||||
| JP538939U |
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)