Title:
INPUT BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JP3739646
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an input buffer circuit for reducing delay time and skew even when the change width of the input signals is small.
SOLUTION: This circuit is provided with a differential amplifier 21 for amplifying the level of signals inputted through a second input terminal N2 with a reference voltage inputted through a first input terminal N1 as a reference and outputting them and a boosting capacitor C connected to the second input terminal N2 of the differential amplifier 21. Further, it is provided with an edge detector 23 for detecting the transition of the output signals of the differential amplifier 21 and a switching part S connected between the first and second input terminals N1 and N2 of the differential amplifier 21 for responding to the output signals of the edge detector 23.
Inventors:
Kim Kei
Lee Jun-pei
Lee Jun-pei
Application Number:
JP2000330959A
Publication Date:
January 25, 2006
Filing Date:
October 30, 2000
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H03K5/12; G11C11/407; H03K19/0175; H04L25/02; (IPC1-7): H03K19/0175; H03K5/12
Domestic Patent References:
| JP63169816A | ||||
| JP6013362A | ||||
| JP6153022A | ||||
| JP11041079A | ||||
| JP10028041A | ||||
| JP10003789A | ||||
| JP9270700A | ||||
| JP7273619A | ||||
| JP5268055A | ||||
| JP57168510A | ||||
| JP2000196680A | ||||
| JP2000114954A |
Attorney, Agent or Firm:
Makoto Hagiwara
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