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Title:
INPUT BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JPH02272909
Kind Code:
A
Abstract:

PURPOSE: To reduce reflection in an external input terminal by impressing a terminating voltage to the source of an MOS transistor, further impressing a suitable voltage to the gate of the MOS transistor and setting the input impedance of a CMOS input buffer to an arbitrary value.

CONSTITUTION: For a CMOS inverter, the complementary pair of a P channel MOS transistor 1 and an N channel MOS transistor 2 are connected and the input end of this CMOS inverter is connected to an external input terminal 4 and connected to the drain of an MOS transistor 7. This MOS transistor 7 determines the input impedance observed from the external input terminal 4 and the gate and source of the MOS transistor 7 are respectively connected to external terminals 5 and 6. By impressing the terminating voltage to the external terminal 6 and impressing the arbitrary suitable voltage to the external terminal 5, the input impedance observed from the external input terminal can be set to the arbitrary value. Thus, the reflection can be reduced in the external input terminal 4.


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Inventors:
IMAMURA KAZUO
OKUBO NAOMI
Application Number:
JP9467389A
Publication Date:
November 07, 1990
Filing Date:
April 14, 1989
Export Citation:
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Assignee:
NEC CORP
NIPPON ELECTRIC ENG
International Classes:
H03K5/00; H03K19/0175; H03K19/0185; (IPC1-7): H03K5/00; H03K19/0175; H03K19/0185
Attorney, Agent or Firm:
Masanori Fujimaki