Title:
INPUT CIRCUIT IN SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH04359560
Kind Code:
A
Abstract:
PURPOSE: To provide the title input circuit capable of restraining the increase in the chip area and the deceleration in speed as well as inversing the TLL input level.
CONSTITUTION: CMOS inverters 5, 6 in multiple stages are connected to an input terminal 1 while the source potential of the p channel transistor of the CMOS inverter 5 in the initial stage is to be made lower than an integrated circuit power supply potential.
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Inventors:
MATSUDAIRA KUNIO
Application Number:
JP16207391A
Publication Date:
December 11, 1992
Filing Date:
June 06, 1991
Export Citation:
Assignee:
RICOH KK
International Classes:
H01L21/8234; H01L27/06; (IPC1-7): H01L27/06
Attorney, Agent or Firm:
Torii Hiroshi