PURPOSE: To prevent an unnecessary through-current from flowing by constituting a titled system so that an input buffer circut inputs an input data by a read instruction signal which is generated from a timing control part, only when a data processing equipment is operated for reading a data from the outside.

CONSTITUTION: An address signal AB for designating a memory address at the time of T1 of a machine cycle M1, synchronizing with a clock signal CLK is outputted to an external bus, and in response to this signal, an instruction code is sent back through a data bus DB from the memory, but a state of DB until it attsins is logically unstable. On the other hand, a timing control part 6 generates a strobe inverting signal RSTB internally in order to read an instruction code from an input buffer circuit 7 in the period of T3, and makes a p-MOS8 and an n-MOS11 to an on-state and an off-state, respectively. As a result, an instruction code which has attained to an input terminal IN before the time of T3 is read into the inside through an inverting circuit formed by a p-MOS9 and an n-MOS10, and is inputted to an instruction register 4 through an internal data bus 3.