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Title:
INPUT AND OUTPUT CIRCUIT IN LOGICAL LSI
Document Type and Number:
Japanese Patent JPS6037820
Kind Code:
A
Abstract:

PURPOSE: To decrease number of required components and to decrease the occupied area by sharing a part of elements for an input/output buffer circuit and a Schmitt circuit through the change of wirings.

CONSTITUTION: The 1st stage inverter consists of PMOSFETs Q1, Q3 and an NMOSFETQ2. A drain terminal of the FETs Q1, Q3 and output nodes n1, n1' are separated, and in constituting the input buffer circuit, the FETQ1 and the node n1 are connected and in constituting the Schmitt circuit, the FETQ3 and the node n1' are connected at aluminum wiring. Thus, an FETQ2 is used in common for both the circuits. On the other hand, the PMOSFETs Q4, Q5 and the NMOSFETQ5 constitute an inverter 2 of the output stage. The drain terminal of the FETQ6 and a node n1" are separated and they are connected together only in constituting the Schmitt circuit.


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Inventors:
SATOU MASAYUKI
YOU KANJI
Application Number:
JP14497583A
Publication Date:
February 27, 1985
Filing Date:
August 10, 1983
Export Citation:
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Assignee:
HITACHI MICROCUMPUTER ENG
HITACHI LTD
International Classes:
H03K19/0185; H03K19/173; (IPC1-7): H03K19/00
Domestic Patent References:
JPS5847323A1983-03-19
JPS5345985A1978-04-25
JPS5710533A1982-01-20
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)



 
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