To shorten the investigating time of a communicating state between a peripheral equipment and a host system, and to facilitate a countermeasure to plural host systems.

A CPU 50 allows an FPGA(Field Programmable Gate Array) 58 to generate a prescribed trace logic circuit, and allows a channel control part 60 to start communication with a host system. The channel control part outputs a channel sequence number 78 through a buffer 62B to the FPGA 58. The FPGA 58 stores a channel interface signal 76 and a channel sequence number 78 in a prescribed timing. When an error is generated in communication, the CPU 50 detects the cause of the error based on the channel interface signal 76 and the channel sequence number 78. When it fails, the detection of the cause of the error is repeatedly operated by allowing the FPGA 58 to generate another trace logic circuit.