Title:
INPUT SIGNAL SYNCHRONIZING PROCESSOR
Document Type and Number:
Japanese Patent JP3487055
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To attain high speed bit synchronization with respect to an input signal synchronizing processor to obtain a bit timing from a received data signal.
SOLUTION: A sampling section 23 calculates a phase of a synchronization clock from a synchronization clock generating section 24 with respect to an edge pulse extracted from an input data signal and stores the result to 1st and 2d memories 25, 26 sequentially, a discrimination section 27 compares the calculated phase with a phase at a preceding sampling to calculate a phase difference. Then the discrimination section 27 allows an adder to obtain a mean value of two phases when the phase difference represents it to be within a range of a data modulation speed, and an arithmetic section 29 calculates a set phase value to the synchronization clock generating section 24 based of the mean value and set the calculated phase to process the synchronization.
Inventors:
Tetsuro Uchida
Application Number:
JP33972995A
Publication Date:
January 13, 2004
Filing Date:
December 26, 1995
Export Citation:
Assignee:
MITSUMI ELECTRIC CO.,LTD.
International Classes:
H04L25/40; H04L7/027; H04L7/033; (IPC1-7): H04L7/033; H04L25/40
Domestic Patent References:
| JP6296184A | ||||
| JP6311155A | ||||
| JP6224875A | ||||
| JP60223224A | ||||
| JP4103238A |
Attorney, Agent or Firm:
Tadahiko Ito
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