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Title:
INRUSH CURRENT LIMITING CIRCUIT
Document Type and Number:
Japanese Patent JPH10243555
Kind Code:
A
Abstract:

To prevent power line terminals and the like from being burnt, by turning on/off according to a specified voltage produced by a current passed through a current-limiting resistor installed between the drain and source of a field-effect transistor, and casing to apply voltage to the gate of the field- effect when of turned on.

When a switch 24 is turned on to charge an input capacitor 25, a current limited by a first current-limiting resistor 27 is passed through the input capacitor 25 until the input capacitance of FET 32 is charged. A current limited by the combined resistance of the first current-limiting resistor 27 and a second current-limiting resistor 33 is passed through the input capacitor 25 until the charging voltage of the input capacitor 25 reaches the working voltage of a relay 26. A current limited by the second current-limiting resistor 33 is passed through the input capacitor 25 during a period from when the voltage of the input capacitor 25 reaches the rated voltage of the relay 26 and to when the voltage is thereafter reduced and a transistor 29 is turned off. As a result, any excessive inrush current is not passed, and power line terminals or line is not burnt.


Inventors:
MIURA KIWA
Application Number:
JP3741497A
Publication Date:
September 11, 1998
Filing Date:
February 21, 1997
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H02H9/02; G05F1/10; H02J1/00; H02M3/00; (IPC1-7): H02J1/00; G05F1/10; H02H9/02; H02M3/00
Attorney, Agent or Firm:
Muneharu Sasaki (3 outside)