Title:
半導体集積回路の検査装置および検査方法
Document Type and Number:
Japanese Patent JP4803568
Kind Code:
B2
Abstract:
A semiconductor integrated circuit inspecting apparatus inspecting a terminal provided on a mount surface of a semiconductor integrated circuit includes a light emitter, a photographing unit and an inspector. The light emitter emits a linear light obliquely to the mount surface. The photographing unit photographs the mount surface to which the light is emitted to output a photograph signal. The inspector inspects the terminal in accordance with the photograph signal. The photographing unit has N (N is a positive integer) photographing elements. The photograph signal is outputted respectively only from M (M is a positive integer smaller than the N) photographing elements of the N photographing elements.
Inventors:
Yoshihiro Sasaki
Masahiko Nagao
Masahiko Nagao
Application Number:
JP2001098739A
Publication Date:
October 26, 2011
Filing Date:
March 30, 2001
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G01B11/02; G01B11/24; G01N21/956; H01L23/12; G01N21/89
Domestic Patent References:
| JP2001188008A | ||||
| JP7174536A | ||||
| JP2001060800A | ||||
| JP2000193432A | ||||
| JP11271030A | ||||
| JP10260006A | ||||
| JP11023234A | ||||
| JP10288505A |
Attorney, Agent or Firm:
Minoru Kudo