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Title:
INSPECTION OF LAMINATION DEFECT AND SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JPH11145228
Kind Code:
A
Abstract:

To provide a method for efficient inspection of a defect in a laminated layer on the surface of a semiconductor wafer in non-destructive manner.

A surface of a semiconductor wafer 1 is conceptually divided into a plurality of cells. A light spot 41 formed on the surface of the wafer 1 is scanned with movement of a stage 10. The cells illuminated with the spot 41 are image picked up by a high-speed image sensor 19 and sequentially stored alternately in image memories 20 and 21 by cell units. An image processor 22 compares the images of the image memories 20 and 21 and finds out a non- matching part therebetween to thereby detect a laminated layer defect present on the surface of the wafer 1. The processor distinguishes between the laminated layer defects and other abnormalities on the basis of the shape of the non- matching part.


Inventors:
NARUOKA HIDEKI
YOSHIDA YOSHIKO
YAMAMOTO HIDEKAZU
Application Number:
JP30555497A
Publication Date:
May 28, 1999
Filing Date:
November 07, 1997
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G01N21/88; G01N21/956; H01L21/66; (IPC1-7): H01L21/66; G01N21/88
Attorney, Agent or Firm:
Shigeaki Yoshida (2 outside)