To provide an inspection method and an inspection device for a semiconductor integrated circuit capable of verifying the quality of a test pattern, by grasping a voltage condition impressed to each transistor, in a reliability test.

A ratio of a stress impression time to total inspection time of times impressed with a prescribed voltage or more of voltage onto a gate oxide film is calculated in the each transistor, and a stress activation rate with respect to the total transistor number constituting the semiconductor integrated circuits of the transistor number in which the calculated stress impression time ratio is larger than a prescribed ratio is calculated, when an SPIC net list indicating the semiconductor integrated circuit of an inspected object, and the test pattern used in a durability test of the gate oxide film in the semiconductor integrated circuit are prepared to conduct SPIC simulation, so as to carry out the durability test for the gate oxide film, based on a result therein. The quality of the prepared test pattern is verified, based on the calculated stress activation rate.