PURPOSE: To speed up a processing by shortening the stage for taking out an instruction.
CONSTITUTION: In a processor 1, decision mechanisms (17 and 19) deciding whether the data of an instruction prefetch buffer 5 to be read is effective or not are provided. When the next instruction is fetched to an instruction fetch register 12, a fetch is performed for the instruction fetch register 12 from the location of an instruction prefetch buffer 5 indicated by the address of the next instruction 'IA+IL' where the address of an instruction address register 2 and the instruction length IL of a micro instruction register 3 are added up to effective data by one fetch based on the decision result of the decision mechanisms. In the decision mechanisms, a signal ONIB deciding whether all the instruction data can be fetched or not is generated and the execution of the instruction is started on this ONIB.
| JPS60103452 | MICROPROGRAM CONTROL SYSTEM |
| JPS57169855 | MICROPROGRAM CONTROLLING SYSTEM |
| JPH04135239 | PIPELINE CONTROL SYSTEM |
KAMISAKA YUJI
NONOMURA KAZUYASU
WATABE TORU
MARUYAMA TAKUMI
KATO SHINYA
POONSHIYAI CHIYONSUWANNAPAISAA
TAKESHITA KATSUNORI
OGURA KIMINARI
