PURPOSE: To provide an instruction mechanism which makes each processor element of a processor process the instructions in parallel.

CONSTITUTION: This mechanism includes an instruction extraction stage BFE which loads the immediately next instruction of an instruction string of a program to be processed to an in instruction buffer memory BPU from a memory CA when the memory BPU that can store (n) pieces of instructions stores is storing instructions less than (n) pieces, an instruction transfer unit BUE which secures correspondence between the instructions BEF stored in the memory BPU and a processor elements PE and produces a selection signal to show the correspondence, a pre-decoding stage BDC, and a conflict check stage KFL which recognizes the conflicts among the instructions to be processed in parallel by the elements PE, and a control signal stage ENG. The stage ENG produces the control signals S-EN of the elements PE from the selection signals and the conflict signals KS and discontinues the instruction processing when a command is received for reception of the instructions BEF or until a conflict is eliminated when it occurs.