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Patent Searching and Data


Title:
INSTRUCTION RECEPTION CIRCUIT
Document Type and Number:
Japanese Patent JPH03219734
Kind Code:
A
Abstract:

PURPOSE: To prevent malfunction due to line quality deterioration in its own line by providing a mark rate modulation instruction demodulation circuit and a parity violation instruction selector switch controlled by a demodulated instruction.

CONSTITUTION: A parity violation(PV) input selection instruction by mark rate modulation (MDM) is inputted to an MDM instruction demodulation circuit 2 by an MDM instruction input 9 and the instruction is demodulated. For example, when an instruction to select its own line input 6 is demodulated, a switch control circuit 3 controls a PV instruction selector switch 4, which is thrown to the position of the PV instruction own line input 6. Then the PV instruction from its own line is inputted to a PV instruction demodulation circuit 5 and the demodulated instruction is outputted to an instruction output 10.


Inventors:
TOMOSUGI TAMIO
Application Number:
JP1461890A
Publication Date:
September 27, 1991
Filing Date:
January 24, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L1/00; H04L1/20; H04L25/02; (IPC1-7): H04L1/00; H04L1/20; H04L25/02
Attorney, Agent or Firm:
Yutaro Kumagai