PURPOSE: To prevent ratching without increasing gate threshold voltage by providing a high impurity concentration region which is the same conductivity type to a collector region in the collector region directly under a source region.

CONSTITUTION: The low impurity concentration and a conductivity type, n+ type, second region (drain or source region) (base region) 2 is provided on the first region (emitter region) 1 made of a p+-type substrate and the p-type third region (collector region) 3 is selectively formed on the surface of the second region 2. Further, the high impurity concentration n+-type fourth region (source region) 4 is selectively formed on the surface of the third region 3. A gate electrode 6 is provided on the fourth region 4 by interposing an insulating film 5 (gate insulating film). A collector electrode 7, an emitter electrode 8 and a p-type high impurity concentration layer 9 are also provided. A high impurity concentration region 10 which is the same conductivity type to the third region 3 is formed directly under the fourth region 4 in the third region 3 by such a method as to implant a high energy p-type ion by using the insulating film 5 which is used for forming the fourth region 4 as a mask before the gate electrode 6 and the collector electrode 7 are provided.