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Title:
INSULATED-GATE FIELD-EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPH06140419
Kind Code:
A
Abstract:

PURPOSE: To obtain an LDD type insulated-gate field-effect transistor of high breakdown strength and large current driving, with a small area.

CONSTITUTION: By forming a diffusion region 20 for preventing field inversion, only in an LDD which is formed in a field insulating layer 12 on the element isolation side, i.e., a second region 19 of a second conductivity type, the diffusion profile of a gate side LDD, i.e., a first region 18 of a second conductivity type can be adjusted, so that the output current and the breakdown strength of a transistor can be set to be the optimum values, to a semiconductor substrate 11 or a well region. The general depth of the diffusion region 20 for preventing field inversion is very large and a high breakdown strength is obtained to a semiconductor substrate or the like, so that the length in the element isolation direction can be reduced in the case of application to an LDD. Thereby an LDD type insulated-gate field-effect transistor of high breakdown strength, large current and small area can be realized.


Inventors:
TAKADA OSAMU
Application Number:
JP28482092A
Publication Date:
May 20, 1994
Filing Date:
October 23, 1992
Export Citation:
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Assignee:
TOSHIBA CORP
TOSHIBA MICRO ELECTRONICS
International Classes:
H01L21/76; H01L21/336; H01L29/78; (IPC1-7): H01L21/336; H01L21/76; H01L29/784
Attorney, Agent or Firm:
Norio Ogo