PURPOSE: To obtain the element of high withstand voltage and a small element area by a method wherein, one each of two sources and drains on two insulated gate field-effect transistors are coupled with each other, in other words, they are placed in the same region.
CONSTITUTION: Two p type regions 15 (P1 and P2) are formed on an n type silicon substrate 19, and an n+ type region 14' which will be turned to two source and drain regions are formed in each p type region 15 respectively. The n+ region 14' which will be turned to one common source and drain region is formed astriding two p type regions and the substrate 19, a gate insulating films 17 are formed on channel regions 20 and 20' and the n+ region 14, and a common gate electrode is provided on the gate insulating film 17. Then, the drain electrode of the left side transistor and the source electrode of the right side transistor are connected. As a result, a metal wiring layer part is unnecssitated, and the measurements between two transistors are reduced. When the gate voltage is in OFF state, the withstand voltage at the p-n junction at two points is almost doubled.
HANEDA HISASHI
SHIMADA YUUKI
NAGANO HITOSHI
NIPPON TELEGRAPH & TELEPHONE