PURPOSE: To enable ON resistance to be reduced without lowering area utilization factor and pressure resistance by providing a control electrode which has an insulation film at the wall face inside a groove in the depth reaching an n--layer from an n+-layer in this groove, and forming a vertical channel reaching the n--layer from the n+-layer.

CONSTITUTION: An n+-layer 2 and an n--layer 3 are formed by epitaxial growth on a P-type water that becomes a P+-layer 1, and P-type impurity is diffused in the whole face of this substrate so as to form a P-layer 4. Next, n-type impurity is diffused, with the oxide film as a mask, so as to form an n+-layer 6 into the specified pattern, and further a groove reaching the n--layer 3 is formed at the main face of the wafer, and after adhering a gate oxide film 7 to the wall face of the groove, low-resistant polysilicon is charged in the groove so as to serve as a gate electrode 8, and an interlayer insulation film 9 is adhered to this upper face, and lastly an emitter electrode 10 is formed by metal deposition, etc. By using such a structure that it has channels in the vertical direction this way, there is no necessity of expanding the unit cell area even for high pressure resistance advancement of an element that the P-layer 4 is formed deep, and ON resistance can be reduced with the same chip area, or high pressure resistance advancement can be realized.