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Title:
INSULATED GATE TYPE FIELD EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPS5494887
Kind Code:
A
Abstract:

PURPOSE: To make channels short by encircling the portions where source and drain layers make contact to substrate with the same conductivity type layer of a concentration higher than that of the substrate.

CONSTITUTION: p type channel stoppers 11 are provided to n type Si and oxide film is opened with holes, where B ions are deeply implanted and driven in to create P+ layers 15,16. Following to this, phosphorus ions are diffused to form n+ layers 17, 18 shallower than 15,16. B ions are implanted to channel parts 23 through gate oxide film 22 to create p+ channels. Electrodes 19 to 21 are provided through Al vapor deposition. With this constitution, threshold voltage is determined only by the B ions of the channel portions because of the p+ layers 15,16 and punch-through may be prevented by the B ions of the layers 17,18 and therefore the short channel MOS of high operating voltage may be formed.


Inventors:
ASAKA MINETOSHI
KOBAYASHI KEIZOU
HAMANO KUNIYUKI
Application Number:
JP248378A
Publication Date:
July 26, 1979
Filing Date:
January 12, 1978
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L29/78; H01L21/336; H01L29/06; (IPC1-7): H01L29/06; H01L29/78
Domestic Patent References:
JPS508484A1975-01-28
JPS51113472A1976-10-06