Title:
INSULATED GATE TYPE SEMICONDUCTOR ELEMENT
Document Type and Number:
Japanese Patent JP3967646
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an insulated gate type semiconductor element enabling improvement of the turn-off characteristics thereof without impairing turn-on characteristics.
SOLUTION: This insulated gate type semiconductor element has a P type emitter layer 1, an N- type high-resistance base layer 3 formed above the P type emitter layer 1, a P type base layer 4 formed in contact with the base layer 3, a gate electrode 7 formed by burying in a trench groove formed at such a depth as bringing it into contact with the base layer 3 in the P type base layer 4, with a gate insulating film 6 interlaid, an N type source layer 5 formed on the surface of the P type base layer 4, in contact with the lateral side of the trench groove, and a second MOS transistor 10 provided for discharging holes outside the element, not through a channel induced by a first MOS transistor which is constituted by the N type source layer 5, the P type base layer 4, the N- type high-resistance base layer 3, the gate insulating film 6 and the gate electrode 7.
Inventors:
Mitsuhiko Kitagawa
Akio Nakagawa
Norio Yasuhara
Tomoki Inoue
Akio Nakagawa
Norio Yasuhara
Tomoki Inoue
Application Number:
JP2002245860A
Publication Date:
August 29, 2007
Filing Date:
March 15, 1994
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L29/78; H01L29/786; H01L21/822; H01L27/04; H01L29/739; (IPC1-7): H01L29/78; H01L29/786
Domestic Patent References:
| JP7135309A | ||||
| JP4131954U | ||||
| JP6037323A | ||||
| JP4093083A | ||||
| JP3058485A |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai