To solve such problem that the reduction of resistance in a current route is limited in an insulation gate-type semiconductor device wherein two element regions are integrated while one substrate is being used as a common drain region, because current flowing between the two element regions detours deep to a semiconductor substrate with low resistance or to a metal layer provided on its backside.
An embedded metal layer reaching an n+-type semiconductor substrate is provided in an n--type semiconductor layer beneath a shield metal layer between two element regions. A part of current detouring around the bottom of the substrate flows shallow around the bottom of the n--type semiconductor layer, so that the current route is partly made short and total resistance of the current route of a device can be reduced. Only an annular region is arranged in a border area between the two element regions to terminate a depletion layer. Thus, a low-resistance layer can be arranged under the annular region, contributing to the reduction of on-state resistance of the device.
ODAJIMA KEITA
ETO HIROKI
SANYO SEMICONDUCTOR CO LTD