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Title:
INTEGRATED CIRCUIT FOR ASYNCHRONOUS SERIAL DATA TRANSFER WITH BIT LENGTH COUNTER
Document Type and Number:
Japanese Patent JP2007202151
Kind Code:
A
Abstract:

To provide an integrated circuit for asynchronous serial data transmission with a bit length counter.

The present invention relates to an integrated circuit (7) for asynchronous serial data transmission having a structure for constituting an input terminal (30) giving asynchronous serial data (d); a scanner (5) scanning the asynchronous serial data (d) by a scan clock (aclk) given to the input terminal; and a bit length counter (4) for determining a bit time by counting the number (m) of scan clocks (aclk) or the number of bit length counter clocks (xclk), wherein a bit length terminal (32) for variably setting the number (m) of clocks of the bit length counter (4) is configured in the integrated circuit (7) and/or the bit length counter (4).

COPYRIGHT: (C)2007,JPO&INPIT


Inventors:
RITTER JOACHIM
Application Number:
JP2007011255A
Publication Date:
August 09, 2007
Filing Date:
January 22, 2007
Export Citation:
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Assignee:
MICRONAS GMBH
International Classes:
H04L25/08; H03K23/66
Attorney, Agent or Firm:
中川 裕幸
反町 行良
大石 裕司
岩田 啓