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Title:
INTEGRATED CIRCUIT DESIGN METHOD
Document Type and Number:
Japanese Patent JP2008071109
Kind Code:
A
Abstract:

To provide an integrated circuit design method whose design development period is short.

This integrated circuit design method comprises a logic design step for mapping a logic cell from the codes of operation description and function description; an arrangement step for arranging logic cells; a wiring congestion estimation step for estimating the place where wiring is congested based on the arrangement information of the logic cells and the number of input/output pins connected to the logic cells; a wiring step for determining the route of wiring; wherein the wiring congestion estimation step can be performed prior to the wiring step.


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Inventors:
MOGI ISAO
MIZUKOSHI TAKASHI
KOJIMA KUNIAKI
NAGAI KAZUKI
MIYA SHIGEO
ASASHIGE HIROKI
Application Number:
JP2006249116A
Publication Date:
March 27, 2008
Filing Date:
September 14, 2006
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F17/50; H01L21/82
Attorney, Agent or Firm:
Shohei Oguri
Toshimitsu Ichikawa
Kimihide Hashimoto



 
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