Title:
INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3295661
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enhance a dynamic range and a response speed in a pixel cell.
SOLUTION: The integrated circuit device is provided with a drive circuit 150 that increase a row reset line voltage of a pixel cell 110 to voltage higher than a power supply voltage VDD. Thus, the reduction in a dynamic range of the pixel cell due to a voltage drop of a threshold voltage (Vth) of transistors (TRs) 112, 113 can be compensated. Charges charged in a capacitor CD (160) are transferred to a parasitic capacitor CRST (195) by turning on a switch DRV and turning off a switch INT. In this case, an inverter boosts s level of a node 161 to a voltage VDD in response to a strobe signal RSTB to increase the row reset line voltage furthermore. The capacitance of the CD is selected while being related to the CRST so that a logic high level of the row reset line is set higher than the VDD by one Vth.
Inventors:
Matthew M Borg
Application Number:
JP34243499A
Publication Date:
June 24, 2002
Filing Date:
December 01, 1999
Export Citation:
Assignee:
AGILENT TECHNOLOGIES, INC.
International Classes:
H03K17/08; H03K17/16; H04N5/355; H04N5/359; H04N5/374; H04N5/376; (IPC1-7): H03K17/08
Domestic Patent References:
| JP6355158A | ||||
| JP9116415A | ||||
| JP6296362A | ||||
| JP5299991A | ||||
| JP7176682A |
Attorney, Agent or Firm:
Kimihisa Kato