PURPOSE: To count a large number with less carry propagation stage number by employing a counter able to count divisors A, B,* of a number having a large number N as a least common multiple so as to count the number Y.
CONSTITUTION: A 1-bit counter A1 and a 1-bit counter A2 form a ternary counter C1 and 1-bit counters, A3, A4 and A5 form a 7-adic counter C2. An output of the ternary counter C1 and an output of the 7-adic counter C2 goes to 1 simultaneously at each of 21 clock periods which is a least common multiple of 3 and 7 and an output of an AND gate G1 goes to 1 at that time. The circuit acts like a 21-adic counter as a whole and a maximum carry propagation stage number is 2. Thus, number of stages of carry propagation is less to count a large number and a high processing speed for the counter is attained.
JP3504316 | MULTI-BIT COUNTER |
JPS59161922 | GRAY CODE COUNTER |