Title:
集積回路装置及びその製造方法
Document Type and Number:
Japanese Patent JP4005762
Kind Code:
B2
Abstract:
The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 mum, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.
Inventors:
Mie Matsuo
Noriaki Matsunaga
Nobuo Hayasaka
Katsuya Okumura
Noriaki Matsunaga
Nobuo Hayasaka
Katsuya Okumura
Application Number:
JP2000189937A
Publication Date:
November 14, 2007
Filing Date:
June 23, 2000
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01F17/00; H01F41/04; H01L23/48; H01L21/822; H01L23/522; H01L23/64; H01L27/04; H01L27/08
Domestic Patent References:
| JP10041470A | ||||
| JP7335439A | ||||
| JP11297927A |
Foreign References:
| WO1996027905A1 |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai