Title:
集積回路装置
Document Type and Number:
Japanese Patent JP4629649
Kind Code:
B2
Abstract:
A shared sense amplifier driver technique for integrated circuit devices including an array of memory cells comprises a plurality of sense amplifiers couplable to the memory cells with each of the sense amplifiers having an associated pull-up and pull-down switching device respectively coupled to a first and second latch node thereof. A first subset of the plurality of sense amplifiers have their first latch node (e.g. latch P-channel "LP") electrically coupled and a second differing number subset of the plurality of sense amplifiers have their second latch node (e.g. latch N-channel "LN") electrically coupled. By sharing the selected LP and LN nodes with more than one sense amplifier in a column, "write" recovery time can be significantly improved over that of conventional layouts and designs.
More Like This:
Inventors:
Michael sey paris
Kim She Hardy
Kim She Hardy
Application Number:
JP2006326329A
Publication Date:
February 09, 2011
Filing Date:
December 01, 2006
Export Citation:
Assignee:
ユナイテッド・メモリーズ・インコーポレーテッド
ソニー株式会社
ソニー株式会社
International Classes:
G11C11/4091; H01L21/8242; G11C7/06; G11C7/18; G11C11/409; H01L27/108
Domestic Patent References:
| JP8255482A | ||||
| JP10188559A | ||||
| JP513713A |
Attorney, Agent or Firm:
Akihiro Ryuka