To suppress external disturbances to bit lines without complicating a memory array and increasing the area.
This integrated circuit 200 has a memory array, of which memory cells 205, 206 are constituted so that a plurality of common bit lines 207 are used in common with many electrically insulated semiconductor regions. Predefined semiconductor regions are typically tubs 203, 204, but the tub is biased to a predefined voltage when a memory cell formed of the tub is accessed for writing operation, and in the other cases, the tub is biased to another voltage. Although many memory cells exist along the same bit line 207, during programming period only selected memory cells are affected by the external disturbances due to the tub bias. Other memory devices in unselected plural tubs are protected from external disturbances the bit lines.
Nobuaki Kato
Shinichi Usui
Takao Ochi
Asahi Shinmitsu