INTEGRATED CIRCUIT MEMORY DEVICE

Title:

INTEGRATED CIRCUIT MEMORY DEVICE

Document Type and Number:

Japanese Patent JPS6089963

Kind Code:

A

Abstract:

PURPOSE: To obtain the titled device which operates by the dynamic memory system by forming a dynamic FF type memory cell with four MISFET's and additionally supplying the leak charges from an accumulation means to the accumulation means through a load means consisting of a high resistance polycrystalline silicone connected to the power supply line.

CONSTITUTION: An IC memory device is formed by providing the MISFET elements Q1 and Q2 for driving, MISFET elements Q3 and Q4 for transmission and load resistances R1 and R2 between the power supply VDD line and word line. Namely, the source of element Q1 is connected to the power supply line VDD throgh the resistor R1, while the drain of element Q2 to the line VDD through the resistor R2 and the drain of element Q1 and source of element Q2 are mutually connected and then arounded. The gate of element Q1 is connected to the reistor R2, while the gate of element Q2 to the reistor R1, and the source and drain of the elements Q3 and Q4 respectively connected to the word line at the gates are respectively connected to the gate of element Q2 and the gate of element Q1.

Inventors:

YASUI NORIMASA
SHIMIZU SHINJI
NISHIMURA KOUTAROU

Application Number:

JP13714584A

Publication Date:

May 20, 1985

Filing Date:

July 04, 1984

Export Citation:

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Assignee:

HITACHI LTD

International Classes:

G11C11/417; H01L21/8238; H01L21/8244; H01L27/092; H01L27/10; H01L27/11; H01L29/78; (IPC1-7): G11C11/40; H01L27/08; H01L27/10; H01L29/78

Attorney, Agent or Firm:

Katsuo Ogawa

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