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Title:
INTEGRATED CIRCUIT PROCESS YIELD ENHANCING TECHNIQUE FOR REDUCING UNDESIRED WATER CONTENT HOLDING OF DIELECTRIC AND HYDROGEN DISCHARGE DIFFUSION INFLUENCE
Document Type and Number:
Japanese Patent JPH10144681
Kind Code:
A
Abstract:

To reduce harmful influence of water content contaminants by passivating an integrated circuit involving a first and second layers to partly absorb contaminants existing on the second layer by the first layer.

An integrated circuit 10 has one element partly surrounded by a first layer, say inter-layer dielectric layer 30 having a relatively high contaminant absorption. This layer 30 is annealed to partly remove water contained therein. A second layer, say, an inter-layer ferroelectric glass layer 34 having a relatively low contaminant absorption is laminated adjacent the dielectric layer 30. On dielectric layer 30 and a ferroelectric glass layer 34, a passivation layer 66 is overlaid to partly absorb any of contaminants existing on the glass layer 34 by the dielectric layer 30.


Inventors:
PERINO STANLEY C
MITRA SANJAY
ARGOS GEORGE JR
HARPER HOLLI
Application Number:
JP27603297A
Publication Date:
May 29, 1998
Filing Date:
October 08, 1997
Export Citation:
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Assignee:
RAMTRON INTERNATL CORP
International Classes:
H01L21/8247; H01L21/316; H01L21/8246; H01L23/00; H01L23/31; H01L27/10; H01L27/105; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/316; H01L27/10; H01L21/8247; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Yoshiki Hasegawa (5 others)