Title:
INTEGRATED CIRCUIT AND SYNCHRONIZATION-TYPE SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3953691
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a synchronization-type semiconductor memory device with an external clock signal.
SOLUTION: A synchronization-type semiconductor memory device is provided with a differential amplifier circuit 202, a dynamic inverter circuit 204, and a clock generation circuit 200 including a reset circuit 206. With this configuration, the clock generation circuit 200 can generate a data clock signal speedily without losing speed when an external clock signal XCLK is inputted and is strong against external noise such as grounding power supply bounding.
Inventors:
Gold pillar
Lee hi spring
Lee hi spring
Application Number:
JP26254599A
Publication Date:
August 08, 2007
Filing Date:
September 16, 1999
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C11/407; G11C7/22; G11C11/4076; G11C11/413; G11C11/417; H03K5/1532; (IPC1-7): G11C11/407
Domestic Patent References:
| JP10172282A | ||||
| JP10240372A | ||||
| JP10208485A | ||||
| JP62118634A | ||||
| JP5242675A | ||||
| JP2018789A | ||||
| JP6333400A | ||||
| JP10093401A | ||||
| JP9214305A | ||||
| JP10144075A |
Attorney, Agent or Firm:
Yasunori Otsuka
Kenichi Matsumoto
Kenichi Matsumoto