Title:
集積回路試験装置及び試験法
Document Type and Number:
Japanese Patent JP3749541
Kind Code:
B2
Abstract:
A testing methodology for very large scale integrated circuits, for example, microprocessors having several million transistors. Initially a set of pseudorandom test patterns is selected. During the design of the integrated circuit it is partitioned into functional units and each unit is designed to be verified and tested by the test patterns. During a test mode all of the units of the integrated circuit receives the test patterns in parallel. The output from each unit is coupled to a signature register. The contents of the signature registers are examined following application of the test pattern. This testing methodology lends itself to the simultaneous testing of many integrated circuits.
Inventors:
Needham, Wayne
Application Number:
JP51847795A
Publication Date:
March 01, 2006
Filing Date:
December 02, 1994
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G01R31/28; G06F11/22; G06F11/267; G01R31/3183
Domestic Patent References:
| JP3125400A | ||||
| JP62021082A | ||||
| JP61296278A | ||||
| JP64010184A |
Attorney, Agent or Firm:
Masaki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Jiro Suzuki
Shigeki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Jiro Suzuki
Shigeki Yamakawa
Previous Patent: ＰＥＤＩＯＣＯＣＣＵＳ属およびＬＡＣＴＯＢＡＣＩＬＬＵＳ属の細菌の...
Next Patent: 少なくとも２の幾何学的に差異をつけたテーパー光学導波管を有する複数...
Next Patent: 少なくとも２の幾何学的に差異をつけたテーパー光学導波管を有する複数...