Title:
INTEGRATED CIRCUIT FOR TRANSMITTER-RECEIVER
Document Type and Number:
Japanese Patent JP3743131
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent the signal of a digital circuit from giving a adverse effects on an analog circuit as a noise, when the analog and digital circuits are integrated on the same chip.
SOLUTION: This circuit is formed by integrating a frequency-converting block to be used for the tuner part of television broadcasting or the like and a PLL block for controlling a local oscillation frequency on the same chip. In this case, the positive and negative power supply terminals of an analog part 22 as the frequency converting block and a digital part 23 as the PLL block are respectively separated, and the analog part 22 and the digital part 23 are separated by providing respective negative side power supply terminals 25 and 27 for the analog and digital, reference potential terminal 38 independent of ground patterns 29 and 33 and reference potential pattern 36 connected on a semiconductor substrate 11 on a semiconductor substrate 21 at the border section of the analog part 22 and the digital part 23. Thus, the effects of the noise at the digital part 23 on the analog part 22 is suppressed.
Inventors:
Toshihiro Yamaguchi
Application Number:
JP21159897A
Publication Date:
February 08, 2006
Filing Date:
August 06, 1997
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H01L21/822; H01L27/04; H03L7/06; H04B1/38; H04B1/3822; (IPC1-7): H04B1/38; H01L27/04; H01L21/822; //H03L7/06
Domestic Patent References:
| JP8274638A | ||||
| JP5284024A | ||||
| JP5109897A | ||||
| JP2251169A | ||||
| JP1206646A | ||||
| JP6037258A | ||||
| JP5047943A | ||||
| JP3003421A | ||||
| JP9017950A |
Attorney, Agent or Firm:
Funabashi Kuninori