Title:
寄生バイポーラトランジスタ作用を減少したMOS構造を有する集積回路
Document Type and Number:
Japanese Patent JP5113317
Kind Code:
B2
Abstract:
An integrated circuit having a MOS structure with reduced parasitic bipolar transistor action. In one embodiment, a MOS integrated circuit device comprises a substrate having a working surface, at least one body region and for each body region a source and a layer of narrow band gap material. Each body region is formed in the substrate proximate the working surface of the substrate. Each layer of narrow band gap material is positioned in a portion of its associated body region and proximate the working surface of the substrate. Each layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate in which each of the body regions are formed. Each source region is formed in an associated body region. At least a portion of each source region is also formed in an associated layer of narrow band gap material.
Inventors:
Besom, James, Day.
Application Number:
JP2003537124A
Publication Date:
January 09, 2013
Filing Date:
October 08, 2002
Export Citation:
Assignee:
Intersil Americas, Inc.
International Classes:
H01L27/088; H01L21/336; H01L29/78; H01L21/8234; H01L27/04; H01L27/092; H01L29/165; H01L29/739; H01L31/12
Domestic Patent References:
| JP9008302A | ||||
| JP7193231A | ||||
| JP2001196586A | ||||
| JP8264785A | ||||
| JP5121738A | ||||
| JP11214627A | ||||
| JP11054748A | ||||
| JP9213926A |
Foreign References:
| WO2001026207A1 |
Attorney, Agent or Firm:
Tadao Hirata