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Title:
INTEGRATED CIRCUIT WITH BUILT-IN MEMORY
Document Type and Number:
Japanese Patent JPS6365547
Kind Code:
A
Abstract:

PURPOSE: To improve the reliability of a memory by providing a means for storing the same information in two addresses and reading it out.

CONSTITUTION: The contents of a nonvolatile memory circuit 1 designated by an address decoder 2 are read out by a read-out/write circuit 3, and on the contrary, the contents of a read-out/write buffer 4 are written in an address of the nonvolatile memory circuit 1 designated by the address decoder 2 through the read-out/write circuit 3. The read-out/write buffer 4 sends and receives a data to and from an external data bus and executes an action for storing temporarily a data. Read-out is executed by a 9-bit unit, read-out is executed continuously two times by a time division format, and a signal for executing such a time division read-out is an address control signal 10. As for write, 18 bits are written simultaneously, but as for an address, two addresses of the nonvolatile memory circuit 1 are utilized, and the same information is written in the respective addresses.


Inventors:
IIDA NORIHIKO
Application Number:
JP21023486A
Publication Date:
March 24, 1988
Filing Date:
September 05, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L27/10; G06F11/10; G06F11/16; G06F12/16; (IPC1-7): G06F11/10; G06F12/16; H01L27/10
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)