Title:
INTEGRATED CIRCUIT WITH CASCODE CURRENT MIRROR
Document Type and Number:
Japanese Patent JPH06252664
Kind Code:
A
Abstract:
PURPOSE: To guarantee a large output voltage by connecting a third bias MOS transistor between a second bias MOS transistor having a drain connected with a first power supply voltage terminal and a second power supply voltage terminal. CONSTITUTION: A bias stage is provided with bias current sources 31 and 32 and a first bias MOSTr41 having a drain connected with the gates of two MOS transistors Tr21 and 23. The gates of the MOSTr21 and 23 are connected through the MOSTr41 and 42 with the gates of MOSTr22 and 24, and the MOSTr41 and 42 form a differential amplifier. Then, the bias stage generates a voltage between the gates of the MOSTr21 and 23 and the gates of the MOSTr22 and 24. The MOSTr21-24 can be biased by the voltage, and the MOSTr21 and 23 can maintain the undistorted current transmission of a cascode current mirror in a saturation mode. At that time, a third bias MOSTr43 is connected between the second power supply terminal 14 and the MOSTr42 so that a large voltage output can be guaranteed.
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Inventors:
EERUKE HOORE
Application Number:
JP1532594A
Publication Date:
September 09, 1994
Filing Date:
February 09, 1994
Export Citation:
Assignee:
PHILIPS ELECTRONICS NV
International Classes:
G05F3/26; H03F1/22; H03F3/343; H03F3/345; H01L27/15; H03F3/347; (IPC1-7): H03F3/343; H01L27/15; H03F1/22; H03F3/345
Attorney, Agent or Firm:
Akihide Sugimura (5 outside)