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Title:
INTEGRATED CIRCUIT WITH INPUT RESISTANCE
Document Type and Number:
Japanese Patent JPH10126244
Kind Code:
A
Abstract:

To obtain a pull-up resistance or pull-down resistance with linear resistance characteristics by providing a pull-up resistance means, which has the gate electrode of a 1st P-type transistor(TR) connected to a 2nd power source or a specific potential developing a gate-source voltage larger than a threshold voltage and the gate electrode of a 2nd P-type TR connected to an input terminal.

The P-type MOS TR P1 has its gate terminal connected to a ground power source Vss or a specific control terminal, which holds the gate-source voltage above the threshold voltage. The P-type MOS TR P2, on the other hand, has its gate terminal connected to the input terminal IN (a). The P-type MOS TR P1 has diode characteristics as shown by a broken line 20, and the P-type MOS TR P2 has diode characteristics shown by a broken line 21. Therefore, when both the P type-MOS TRs P1 and P2 are put together, the input current Iin has nearly linear characteristics like the solid line 22.


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Inventors:
KONO TAKAO
Application Number:
JP27506696A
Publication Date:
May 15, 1998
Filing Date:
October 17, 1996
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L27/04; H01L21/822; H03K19/0175; H03K19/0944; (IPC1-7): H03K19/0175; H01L21/822; H01L27/04; H03K19/0944
Attorney, Agent or Firm:
Kenji Doi (1 person outside)